71. G. S. Lin and you will J. B. Kuo, “Fringing-Created Slim-Channel-Impression (FINCE) Associated Capacitance Behavior out of Nanometer FD SOI NMOS Products Having fun with Mesa-Separation Thru three-dimensional Simulation” , EDSM , Taiwan ,
72. J. B. Kuo, “Progression regarding Bootstrap Techniques in Lower-Current CMOS Digital VLSI Circuits getting SOC Apps” , IWSOC , Banff, Canada ,
P. Yang, “Gate Misalignment Feeling Related Capacitance Conclusion from an effective 100nm DG FD SOI NMOS Device with n+/p+ Poly Top/Base Door” , ICSICT , Beijing, China
73. G. Y. Liu, Letter. C. Wang and J. B. Kuo, “Energy-Productive CMOS High-Load Rider Circuit into the Complementary Adiabatic/Bootstrap (CAB) Technique for Lowest-Power TFT-Liquid crystal display System Software” , ISCAS , Kobe, The japanese ,
74. Y. S. Lin, C. H. Lin, J. B. Kuo and K. W. Su, “CGS Capacitance Technology away from 100nm FD SOI CMOS Gadgets which have HfO2 High-k Entrance Dielectric Offered Vertical and you can Fringing Displacement Consequences” , HKEDSSC , Hong kong ,
75. J. B. KUo, C. H. Hsu and you can C. P. Yang, “Gate-Misalignment Related Capacitance Behavior away from a beneficial 100nm DG SOI MOS Products with N+/p+ Top/Base Entrance” , HKEDSSC , Hong-kong ,
76. G. Y. Liu, N. C. Wang and you can J. B. Kuo, “Energy-Effective CMOS High-Stream Rider Circuit on the Subservient Adiabatic/Bootstrap (CAB) Way of Reasonable-Fuel TFT-Liquid crystal display Program Apps” , ISCAS , Kobe, Japan ,
77. H. P. Chen and you will J. B. Kuo, “A great 0.8V CMOS TSPC Adiabatic DCVS Reasoning Routine for the Bootstrap Method to have Low-Electricity VLSI” , ICECS , Israel ,
B. Kuo, “A book 0
80. J. B. Kuo and you may H. P. Chen, “The lowest-Current CMOS Load Rider towards the Adiabatic and you can Bootstrap Techniques for Low-Fuel System Software” , MWSCAS , Hiroshima, The japanese ,
83. Yards. T. Lin, E. C. Sun, and J. B. Kuo, “Asymmetric Gate Misalignment Influence on Subthreshold Functions DG SOI NMOS Equipment Offered Fringing Digital Field-effect” , Electron Gadgets and Thing Symposium ,
84. J. B. Kuo, Age. C. Sunrays, and you can Meters. T. Lin, “Data away from Entrance Misalignment Influence on this new Endurance Voltage off Twice-Door (DG) Ultrathin FD SOI NMOS Products Playing with a tight Design Offered Fringing Electric Field effect” , IEEE Electron Devices having Microwave and you can Optoelectronic Applications ,
86. Age. Shen and you may J. 8V BP-DTMOS Articles Addressable Memories Mobile Routine Based on SOI-DTMOS Process” , IEEE Meeting to your Electron Gizmos and Solid state Circuits , Hong-kong ,
87. P. C. Chen and J. B. Kuo, “ic Logic Routine Having fun with an immediate Bootstrap (DB) Way of Lower-voltage CMOS VLSI” , Global Symposium towards Circuits and you may Assistance ,
89. J. B. Kuo and you will S. C. Lin, “Lightweight Description Design getting PD SOI NMOS Products Considering BJT/MOS Effect Ionization to possess Spice Circuits Simulator” , kissbrides.com my latest blog post IEDMS , Taipei ,
90. J. B. Kuo and S. C. Lin, “Compact LDD/FD SOI CMOS Equipment Model Considering Opportunity Transport and Care about Heat getting Spice Routine Simulator” , IEDMS , Taipei ,
91. S. C. Lin and J. B. Kuo, “Fringing-Induced Hindrance Lowering (FIBL) Outcomes of 100nm FD SOI NMOS Equipment with a high Permittivity Door Dielectrics and you may LDD/Sidewall Oxide Spacer” , IEEE SOI Conference Proc , Williamsburg ,
ninety five. J. B. Kuo and you may S. C. Lin, “The fresh Fringing Electric Field-effect into Short-Station Perception Tolerance Current out of FD SOI NMOS Gadgets that have LDD/Sidewall Oxide Spacer Framework” , Hong-kong Electron Equipment Appointment ,
93. C. L. Yang and you can J. B. Kuo, “High-Temperature Quasi-Saturation Brand of Large-Current DMOS Stamina Equipment” , Hong kong Electron Devices Fulfilling ,
94. Age. Shen and you may J. B. Kuo, “0.8V CMOS Stuff-Addressable-Memories (CAM) Cell Ciurcuit that have a simple Mark-Compare Possibilities Playing with Majority PMOS Dynamic-Tolerance (BP-DTMOS) Strategy According to Standard CMOS Technology to possess Reasonable-Voltage VLSI Possibilities” , In the world Symposium towards the Circuits and Options (ISCAS) Legal proceeding , Arizona ,
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